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First ACM SIGPLAN Workshop on Languages, Compilers, and Hardware Support for Transactional Computing

PLDI 2006

Ottawa, Canada, June 11, 2006

::Invited Talk::

Nesting Transactions: Why and What do we need?
Eliot Moss, University of Massachusetts Amherst

We are seeing many proposals supporting atomic transactions in programming languages, software libraries, and hardware, some with and some without support for nested transactions. I argue that it is important to support nesting, and to go beyond closed nesting to open nesting. I will argue as to the general form open nesting should take and why, namely that it is a property of classes (data types) not code regions, and must include support for programmed concurrency control as well as programmed rollback. I will also touch on the implications for software or hardware transactional memory in order to support open nesting of this kind.

Invited talk

Nesting Transactions: Why and What Do We Need?    [slides]
Eliot Moss

Software Transactions   Chair: David Tarditi

Lowering the Overhead of Nonblocking Software Transactional Memory    [slides]
Virendra J. Marathe, Michael F. Spear, Christopher Heriot, Athul Acharya, David Eisenstat, William N. Scherer III, and Michael L. Scott

Snapshot Isolation for Software Transactional Memory   [slides]
Torval Riegel, Christof Fetzer, and Pascal Felber

What Really Makes Transactions Faster?  [slides]
Dave Dice and Nir Shavit

Debugging with Transactional Memory   [slides]
Yossi Lev and Mark Moir

Hardware Transactional Memory     Chair: Christos Kozyrakis

Hardware Acceleration of Software Transactional Memory   [slides]
Arrvindh Shriraman, Virendra J. Marathe, Sandhya Dwarkadas, Michael L. Scott, David Eisenstat, Christopher Heriot, William N. Scherer III, and Michael F. Spear

Extending Hardware Transactional Memory to Support Non-Busy Waiting and Non-Transactional Actions   [slides]
Craig Zilles and Lee Baugh

Language Design, Specifications, and Analysis   Chair: Dan Grossman

Transactional Memory with Data Invariants   [slides]
Tim Harris and Simon Peyton Jones

Sequential Specification of Transactional Memory Semantics   [slides]
Michael L. Scott

Lock Inference for Atomic Sections  [slides]
Michael Hicks, Jeffrey S. Foster, and Polyvios Pratikakis

Higher-Order Combinators for Join Patterns Using STM   [slides]
Satnam Singh



The goal of this workshop is to provide a forum for the presentation of research on all aspects of transactional computing. There has been much recent interest on extending programming languages, systems, and hardware with support for transactions, speculation, and related abstractions that provide alternatives to classical lock-based concurrency mechanisms. The goals of this workshop should be construed broadly to include any novel software or hardware techniques, algorithms, or implementations for transactional concurrency abstractions applicable to multi-core, multithreaded, or high- performance parallel systems. This workshop is intended to cover foundations of concurrent programming as it relates to all forms of transactional computing, as well as tools, techniques, and applications that leverage these principles. Experience reports are also welcome.


The workshop seeks papers on topics related to all areas of software and hardware for new concurrency abstractions, models, and implementations. Topics of interest include (but are not limited to):

  • Transactional Memory
  • Hardware support
  • Atomicity
  • Non-blocking algorithms
  • Memory models
  • Checkpointing
  • Debugging
  • Semantics and verification
  • Static analysis and Compiler optimizations
  • Runtime implementations
  • Persistence and I/O
  • Speculative concurrency
  • Applications

Papers should present original research relevant to any of these areas of concurrent programming and should provide sufficient background material to make them accessible to the broader community. Papers focussed on foundations should indicate how the work can be used to advance practice; papers on experiences and applications should indicate how the experiments reinforce principles.

::Important dates::

Submissions due: March 1.
Notification: April 15.
Final version : May 15.

::Paper submission::

Papers must be submitted in Postscript or PDF format. Hard copies of all research presentations and position papers will be distributed at the meeting. The conference web page will make available all slides from presentations given by the attendees, but the conference web page will not host papers. This is to ensure that the workshop is correctly understood to be an informal workshop, and that presentation of research at the workshop is not considered a barrier to republication of that research in conferences. Papers should be clearly labeled as either:

  1. Research papers: These papers present new results which have not appeared and are not under submission elsewhere. These papers should not exceed 10 pages in ACM double column format.
  2. Position/Experience papers: Short papers (<5 pages in ACM format).

The submission site is here.

A special journal issue is being considered with a selection of the best research papers.


Program Committee:

Cliff Click, Azul
Laurent Daynes, Sun
Rick Hudson, Intel
Stephen Freund, Williams
Dan Grossman, Washington
Suresh Jagannathan, Purdue
Christos Kozyrakis, Stanford
Peter O'Hearn, Queen Mary, U. of London
Bill Pugh, UMaryland
Ravi Rajwar, Intel
Nir Shavit, Sun
David Tarditi, Microsoft
Mandana Vaziri, IBM

General Chair:
Jan Vitek, Purdue

Program Chair:
Suresh Jagannathan, Purdue

Steering Committee:
Tim Harris, Microsoft
Maurice Herlihy, Brown
Tony Hosking, Purdue
Doug Lea, SUNY, Oswego
Eliot Moss, UMass
Jan Vitek, Purdue

::Related Events::

Workshop on Transactional Memory Workloads